Field of the Invention
The present invention relates generally to data processing systems. Aspects of the invention are concerned with the detection and/or indication of events which may occur during operation of such systems and the timing of operations performed by such systems.
The various aspects of the invention can be applied, though not exclusively, in the field of digital audio data processing such as may be performed by the signal processing rack in an audio recording studio. The invention will be illustrated hereinafter with particular reference to such an application, though it is to be appreciated that the invention can be applied to other data processing systems.
In an audio recording studio, as illustrated by the simplified block diagram of FIG. 1, the signal processing rack 1 communicates with an operator console 2 and, as indicated by the LINK & I/O block 3, is also connected into the studio network for communication of audio and control data between the signal processing rack and the various input/output devices, e.g. speakers, microphones, DATs etc., connected to the network link. Operation of the network is controlled at the console, or mixing desk, 2, communication of data between devices in the network and implementation of the necessary processing by the signal processing rack being performed in response to operation of the console controls.
The signal processing rack 1 can be considered to be divided into a control side, which is responsive to the status of the various controls on the console 2, and an audio processing side which implements the required audio processing functions in dependence upon the control settings and communicates audio data with the network devices via the link.
In one example of a signal processing rack 1 to which the invention can be applied, the processing of digital audio data is performed by a parallel processing array as illustrated schematically in FIG. 2 of the accompanying drawings. FIG. 2 shows an array of eight signal processing integrated circuits (SPICs) 4 labelled A to F. The SPICs, or data processors, 4 are arranged at least electrically in a rectangular array, each SPIC being connected to a horizontal data bus H and a vertical data bus V. Each SPIC 4 is arranged for communication of data with each of the two buses to which it is connected, each of the horizontal and vertical buses H,V being shared by a number of SPICs 4.
The parallel processing array as a whole of course consists of a substantially greater number of SPICs than shown in FIG. 2. The SP rack 1 in fact includes up to 16 cards, each card carrying an array of, for example, eight SPICs. The horizontal and vertical buses are connected between cards, so that, electrically, the SPICs form one large rectangular array. The buses may be connected in a loop, with periodic pipeline registers, for example every four cards, to allow bi-directional communication around the loop and extend the processing power of the array.
The SPICs 4 in the array run synchronously, each SPIC performing a sequence of operations in each audio sample period in accordance with an instruction sequence stored in an internal memory. The SPICs are pre-programmed with the instruction sequences at set-up so that all possible required processing operations can be implemented by the array. In one particular example, each SPIC is preprogrammed with 512 instructions, successive instructions being read from the internal memories for implementation by the SPICs in successive cycles of a clock signal. A control processor (not shown) is provided on each card for controlling various aspects of the operation of the SPICs on that card. In operation, the SPICs run synchronously through their instruction sequences under control of the control processors, the control processors being responsive to the operator console 2 to cause the SPICs to implement the various processing operations as required.
During operation of the system, it is necessary for the control processor controlling an array of SPICs to be alerted to the occurrence of certain events, eg the occurrence of an error condition such as a signal overload or a parity error. As a further example, part of the pre-programmed operation of some of the SPICs may be to implement timers for various purposes, eg to set the time for which an indicator is to be lit on the operator console, and the control processor must be alerted to the expiry of such timers to perform the appropriate control function. The SPICs can of course be configured to transmit signals to the control processor on occurrence of such events. However, since each SPIC performs numerous (eg many hundred) processing operations in each audio sampling period, the tasks of generating such signals and identifying the sources of the signals must be implemented as simply and efficiently as possible if overall efficiency of the processing system is to be achieved.
As part of their operation, the SPICs need to able to process audio data in accordance with control signals received by the control processor from the operator console 2 indicating the setting of the various console controls. For example, if a control setting for signal level is changed, audio signals processed by the SPICs will need to be multiplied by different values, or coefficients, to change the actual audio signal level. The sampling frequency of control signals derived from the operator console is generally considerably lower than the audio sampling frequency, e.g. 1 kHz or lower as compared with 50 kHz. Interpolation of the control signals is therefore required to obtain a gradual change in the value of coefficients over the multiple audio samples within one period of the control signal sampling frequency. To implement this, a coefficient interpolator may be associated with each SPIC. The control processor calculates coefficient data in accordance with the control signals from the console, and periodically supplies the coefficient data to the interpolator. The interpolator uses the coefficient data to derive interpolated coefficients for use by the associated SPIC. The period over which coefficients are interpolated is determined by a coefficient sampling rate signal (CSR signal) supplied to the interpolator. In practice there are a number of such CSR signals, with different clock rates, provided in the system so that interpolation can be performed in accordance with different ones of the CSR signals as required for different purposes.
In general, coefficient data calculated by the control processor will need to be supplied to more than one SPIC for updating the coefficients used in processing operations, and it is important to ensure that the new coefficient data is supplied to the relevant SPICs so that they start using the new coefficient values in the same audio sample period. For example, as part of their function the SPICs may implement various multi-tap or multi-pole filters, and updated coefficients for these filters must be introduced sample-synchronously to avoid distortion. Thus, it is necessary to provide a convenient way of timing the updates to coefficient data supplied to the interpolators.